Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...

Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching ...

In design verification, one size does not fit all. What works on the enterprise level may not work for the design team or individual designer, and vice versa. On the heels of its acquisition of ...

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...

While IC design complexity increases, the amount of time allotted for designing ICs remains about the same. That compels engineers to accelerate all the processes involved. I’m a member of a team that ...